The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit which is composed of an LSI circuit fabricated on one chip and capable of selective interfacing on different interface levels for an increased number of functions and a higher degree of circuit integration.
Description of the Related Art:
Recent semiconductor integrated circuit fabrication technology makes it possible to provide more than one million transistors on one chip due to advanced scaling down of MOS transistor device size. Bi-CMOS integrated circuits which are composed of bipolar devices and CMOS devices put together on one chip for combined characteristics thereof are finding wide use. Bi-CMOS integrated circuits may be combined with a high-speed ECL (Emitter-Coupled Logic) and a low-power CMOS circuit to realize a logic circuit which can operate at high speed and has low power requirements.
Efforts have been made to fabricate a high-speed, low-power semiconductor static memory using a Bi-CMOS integrated circuit. For example, Collected Papers C-699 of Lectures for Spring National Convention, Electronic Information Communications Society, 1990 show a semiconductor static memory comprising a Bi-CMOS integrated circuit as an LSI circuit. The disclosed semiconductor static memory uses, as input/output interface levels, an ECL level having a small logic amplitude of about 0.8 V and capable of transferring signals at high speed. Since the LSI circuit is a low-power CMOS integrated circuit, it is necessary to convert an input signal with ECL levels to a signal with CMOS levels whose logic amplitude is approximately equal to a power supply voltage.
Conventional semiconductor static memories, constructed as semiconductor integrated circuits, with ECL and CMOS interfaces are substantially identical in circuit arrangement except for those interfaces. However, since the semiconductor static memories are designed and manufactured as different integrated circuits, they cannot be designed and manufactured with efficiency.
Some high-performance computer systems require cache memories for an exchange of information between a CPU which operates at high speed with ECL levels and a main memory which comprises an inexpensive, large-capacity DRAM operating with CMOS levels or TTL levels. Therefore, the cache memories should transfer signals between different interface levels.